Samarth Narang

• One of the core contributors to a new MLIR-based compiler stack for Qualcomm’s AI inference on Hexagon NPUs. Played a key role in prototyping phases and benchmarking of the Triton-based compilation path.
• Part of the team that extended a sequence of MLIR passes including multi-level tiling, fusion, vectorization, and multithreading, culminating in lowering to llvm for NPU backend codegen.
• Working on tiling algorithms used by Qualcomm's proprietary Hexagon NPU Compiler to facilitate on-device AI inference.
• Periodically handle critical performance issues faced by customers while running LLMs on Qualcomm NSPs.

ML Compiler Backend Development

• Collaborated in the development of an AI compiler for DeGirum's hardware accelerator, focusing on performance and extending the reach of compatible models.
• Implemented SIMD parallelism, vector processing, and pipeline strategies to minimize data movement and memory footprint.
• Expanded the existing compiler to support Large Language Models (LLMs) through in-depth understanding of Transformer-based architectures.
• Benchmarked CPU cores using FPGA to offload certain operations in real-time execution of models.

ML Deployment Infrastructure

• Compiled ML models using the DeGirum compiler and orchestrated their seamless integration within the DeGirum Ecosystem.
• Leveraged Flask API for robust and efficient integration, ensuring smooth communication between components.
• Developed comprehensive unit tests utilizing the PyTest framework.
• Implemented CI/CD pipelines to establish an automated workflow for deployment and testing processes.

Machine Learning Team (08/16/22 - 05/30/23)

• Worked extensively with the PyTorch framework to compile deep learning models on company specific compilers.
• Facilitated Quantization for models from FP32 to UInt8 precision to expand the variety of model choices.
• Successfully ported 132 models (both quant and float) from the popular timm repository to DeGirum's Model Zoo.
• Created custom Python modules and packages to facilitate code reuse and maintainability.

Embedded SW Team (02/01/22 - 08/15/22)

• Built a UART interface monitor using RISC-V Assembly for field engineers as a debug tool.
• Developed ROM code routines for MBIST operations.
• Redesigned existing MBIST testing code to decrease test completion time by 40%.
• Implemented a series of embedded C tests for Pre-Silicon RTL validation.
• Refactored and expanded functionality of the Verilog Test Bench.